“Our goal is to provide our customers with higher performance PLLs, while reducing their SoC die size, cost, and EMI. In many of today’s SoC’s, a high frequency clock is already available. In such cases, our SS technology enables the SoC designer to generate a spread-spectrum version of that clock, without the need for the large loop filter that consumes most of the area of a traditional SS-PLL implementation. Additionally, this modularity simplifies implementation of standards where spread-spectrum is an optional feature, such as PCI-E and SATA,” said Ashraf Takla, Mixel President and CEO. “The HPPLL offers superior output frequency granularity and 50% duty cycle for both even and odd output divisors at lower power consumption. These are clear differentiating factors that Mixel brings to its customers and partners today,” he added.

Mixel will be using this SSPLL technology to offer spread-spectrum option in its PCI-Express and SATA IPs. The MXL-PLL-SS and MXL-PLL-SYN-HP are offered in 0.13um and 0.18um process technologies and soon will be offered in smaller feature sizes.