LVDS De-serializer Architecture:



The MXL-DS-LVDS is a high performance 4-channel LVDS De-serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components. Great care was taken to insure matching between the Data and Clock channels to maximize the de-serializer margin. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.

The Mixel SerDes LVDS Features:

  • 25-165 MHz clock support
  • Up to 1.15 Gbps bandwidth
  • Up to 5 Gbps data throughput
  • Low power CMOS design
  • Power Down mode
  • Low swing LVDS devices for low EMI
  • PLL requires no external components
  • Programmable parallel data width
  • Compatible with TIA/EIA-644 LVDS Standard

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