LVDS Serializer Architecture:


1.0Gbps operation


1.2Gbps operation


1.6Gbps operation Beyond specification

The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components. It employs optional pre-emphasis to enable transmission over a longer distance while achieving low BER. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.

The Mixel SerDes LVDS Features:

  • 25-165 MHz clock support
  • Up to 1.25 Gbps bandwidth
  • Up to 5 Gbps data throughput
  • Low power CMOS design
  • Low swing LVDS for low EMI
  • PLL requires no external components
  • Core Voltage & 3.3V dual power supply
  • Optional transmit pre-emphasis
  • Programmable parallel data width
  • Rising/falling edge data strobe
  • Compatible with TIA/EIA-644 LVDS Standard

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