D-PHY

D-Phy Architecture:

D-PHY_Architecture

1st generation running up to 1.0Gbps

1.0Gbps 2008_Chip

2nd generation running up to 1.5Gbps

1.5Gbps 2010-Chip

3rd generation running up to 2.5Gbps

Mixel’s D-PHY is a complete PHY, silicon-proven at multiple foundries. The D-PHY is fully integrated and has analog circuitry, digital, and synthesizable logic. Our D-PHY is built to support the MIPI® Camera Serial Interface (CSI), Display Serial Interface (DSI) and Unified Protocol (UniPro™) using the PHY Protocol Interface (PPI).

The Mixel D-PHY features:
  • The D-PHY uses point-to-point differential interface and has modular architecture supporting multiple data lanes and a clock lane allowing all possible configurations
  • Mixel’s D-PHY data lanes support both bidirectional and unidirectional modes, Clock lane supports unidirectional communication
  • Supports CSI-2, DSI, and Unipro™
  • The D-PHY supports 80Mbps to 1.5Gbps data rate in high speed mode, 10Mbps data rate in low-power mode
  • Mixel’s D-PHY can be configured to operate as a slave or a master.
  • Support data rates from 80Mbps to 2.5Gbps

Mixel’s D-PHY is architected to mate perfectly with our high performance PLLs specifically designed to address MIPI applications up to 2.5Gbps.