Mixel Achieves Full-Chip Verification of a Programmable 3.2Gbps Quad Transceiver IP with Infinisim RASER
“Verifying functionality at full-chip level gives designers much-needed confidence that the silicon will come back working. Current simulators are running out of steam to handle full-chip verification. Mixel’s experience is a clear example of why mixed-signal designers need our RASER simulator”
The 3.2Gbps quad-lane SerDes IP is capable of supporting 1.0 to 3.2 Gbps operation in each of four channels. It is compatible with router-backplane links, PCI Express, 10Gbps Ethernet (XAUI), Fibre Channel, SFI-5, SPI-5 and a variety of other communication applications. The programmability derives from the ability to choose from several multiplication factors supported by the integrated frequency synthesizing PLL. Unique features include programmable TX amplitude, TX-pre-emphasis, RX equalizer, and programmable width of the parallel interface. This chip required very accurate simulation due to the low jitter requirements at high speeds. Conventional simulators could not verify the complete functionality due to the chip’s size. RASER was able to quickly verify this mixed-signal chip with true SPICE accuracy.
“We have never been able to do full-chip verification at SPICE accuracy with existing tools before. However, with RASER, we were able to verify the full-chip functionality within one day,” said Yude Liou, Director of Engineering at Mixel Inc. “Verifying mixed-signal IP functionality at the top level is important for us because this is the best way to insure first-time success. In addition to functionality checking, RASER opens the door for doing extensive Monte Carlo analysis at the top-level and with larger blocks than we were able to run before.
Running Monte Carlo with larger blocks gives us better confidence that functional pieces work together with high yield. It also gives us a clearer picture of actual performance over process variation without having to over-design small blocks. Using RASER enabled us to rapidly evaluate the performance of the IP at the top level. This is part of our ‘First-time functional silicon is the rule; no exception’ methodology.”
“Delivering outstanding mixed-signal IP solutions requires outstanding mixed-signal tools. Choosing best-of-class tools is one of the many strategies that Mixel employs to maintain profitability and growth in a competitive market,” said Ashraf Takla, Mixel CEO. “Infinisim’s RASER fits well with Mixel’s robust design methodology. It enables us to rapidly gain a high level of confidence that performance of our IP consistently exceeds our customer’s expectations.”
Mixel selected RASER after a thorough evaluation of several SPICE simulators, both existing and new technologies. Mixel found that RASER delivered true SPICE accuracy and achieved orders-of-magnitude better capacity and performance. Mixel currently uses RASER to verify all of its designs.
“Verifying functionality at full-chip level gives designers much-needed confidence that the silicon will come back working. Current simulators are running out of steam to handle full-chip verification. Mixel’s experience is a clear example of why mixed-signal designers need our RASER simulator,” said Ms. Samia Rashid, President of Infinisim. “We are delighted that leading-edge companies like Mixel are choosing RASER for their challenging full-chip verification.”
Mixel is the leader in mixed-signal mobile IPs and offers a wide portfolio of high-performance, mixed-signal connectivity IP solutions. Mixel’s mixed-signal portfolio includes Mobile PHYs (MIPI D-PHY, M-PHY, and MDDI), PHYs and SerDes (suitable for PCI Express, SATA, EPON, XAUI, Fiber Channel, DDR, and LVDS), general purpose transceivers, and high-performance PLL, DLL IP cores. For more information contact Mixel at email@example.com or visit www.mixel.com.
Infinisim provides guaranteed SPICE-accurate simulation results with an average of 50 times higher throughput and capacity for large circuits. Our patent pending Real-time Adaptive Simulation™ (RAS™) technology makes the simulator always accurate and always fast. Used in both pre- and post-layout detailed circuit verification, Infinisim’s simulator RASER is highly effective for large scale analog mixed-signal and advanced digital designs. RASER’s speed and capacity uniquely position it for handling simulations of large blocks and entire ICs. Infinisim has enabled its customers to eliminate silicon respins, reduce chip design schedules and dramatically improve product quality and production yield. For more information about Infinisim, please visit the company’s website at http://www.infinisim.com.
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