Join Mixel at Siemens U2U where we will present, “Enhancing IP QA flow using Solido Crosscheck,” based on our experience with MIPI D-PHY, C-PHY, M-PHY, and other mixed-signal IPs.
Design IPs play a crucial role in the design and development of modern SoC (System on Chip) designs, and have increased in usage with the rapid evolution and complexity of modern designs. These pre-designed, pre-verified blocks help designers achieve faster design cycles with improved reliability. The modular approach of design IPs enables reuse, thereby reducing development cost. Utilizing well-validated and qualified design IPs can ensure SoCs meet industry standards and specifications, and achieve a high level of quality.
Design IPs can be represented in various views and formats, including (a) front-end views including Verilog, VHDL, .libs, and SDF, (b) back-end views including LEF, DEF, and GDS, (c) schematic views such as SPICE and Spectre, and a variety of other views. These different views and formats can originate from multiple sources in the design process, making it crucial to ensure their consistency with each other. Because of this, lack of an effective IP QA flow can lead to higher risk of design failure, sub-optimal performance, and tape-out delays.
A robust IP QA framework should possess the following capabilities:
- Design- and technology-agnostic IP QA: The framework should focus on identifying issues early in the flow, regardless of the underlying design methodology or technology node being used.
- Comprehensive validation coverage: The validation methodology should cover a wide range of checks to ensure thorough verification.
- Adaptability to changing specifications: Performance and specifications may change at each revision made to the design IP. Therefore, the QA methodology must have the ability adapt to these changes.
- Flexibility for adding functionality: To support a wide range of use cases, the QA methodology should be extensible, and allow for the addition of custom functionality to complement existing built-in checks.
Our paper explores the enhancement of Mixel’s in-house IP QA flow with the use of Solido Crosscheck. We will delve into how syntax checks, in-view and cross-view consistency checks, timing arc checks, and layout versus layout (LEF versus GDS) comparisons help to address potential issues early in the design flow, and improve the overall IP quality.
Authors
- Amr Shehata (Mixel, Inc.)
- Muhammad A. Halim (Mixel, Inc.)
- Lionel Coulder (Siemens EDA)
- Siddharth Ravikumar (Siemens EDA)
