Job Code

• EG-FPGA-01

Location

• Cairo, Egypt

About the Job

• Develop a thorough understanding of system-level design specifications.​
• Hardware verification of the digital module using cutting-edge FPGA kits.
• Develop RTL code of system-level layers integrating Mixel MIPI IPs.​
• RTL Synthesis/FPGA P&R of the digital part of Mixed-Signal IPs.​
• Design and implement hardware verification activities through simulation environments and lab tests.
• Working with the validation team on the testing/characterization and prototyping of Mixel IPs.

Job Requirements

• Bachelor’s degree in Electronics Engineering. Master’s Degree is a plus
• 0-4 Years of experience in Digital Design/Verification
• Strong knowledge of Verilog RTL design/simulation
• Knowledge of FPGA design flows including RTL Synthesis, Place and Route, and Timing Sign-off.
• Knowledge of gate-level verification techniques ​
• Desirable Qualifications and Experience:
  • • Familiarity with System Verilog, RTL/gate verification techniques is a plus
    • Familiarity with FPGA kits and FPGA hardware interfaces is a plus
    • shell scripting/programming languages.
    • Unix/Linux operating systems.