Digital Verification Development Senior Team Lead

Full-Time
Egypt
Posted 3 weeks ago

Job Code

  • EG_ ASIV_05

Location

  • Cairo, Egypt

About the Job

  • Team planning and team member resource utilization.
  • Hands-on experience with employing constrained-random coverage driven verification methodology using UVM
  • Participating in deploying new methodologies to improve coverage and execution time in collaboration with other experienced engineers on the team
  • Working with the design team to validate and verify any requested design changes throughout the project life cycle.
  • Develop a thorough understanding of system-level design specifications. 
  • RTL Coding/Synthesis of the digital part of Mixed-Signal IPs. 
  • Develop behavioral models for the analog parts of Mixed-Signal IPs. 
  • Working with the verification team to develop advanced test plans. 
  • Working with the Mixed-Signal team on the co-simulation and verification of the IPs. 
  • Hardware verification of the digital module using cutting-edge FPGA kits.
  • Coach your team members in a way that strengthens two-way communication and reinforces desired behaviors.
  • Monitor the project’s load on the team members and act/organize accordingly, to remove stress, or retain balance/fairness in the distribution of workload after agreement with Project Leads, and Team Manager.
  • Communicating team goals and identifying areas for new training or skill checks.
  • Develop the Training and Development needs for each employee, and Agree on a development plan to help them improve their performance and support the organization’s success.
  • Motivates others by setting a good example and appreciates/provides encouragement to the ongoing effort of the team members.

Job Requirements

  • B.Sc. or M.Sc. in Electronics Engineering
  • 7+ Years of experience in developing SV-based verification environments. 
  • Strong knowledge of Verilog, System Verilog, and object-oriented 
  • Computer skills required: Unix/Linux operating system
  • Strong knowledge of Verilog, System Verilog, and object-oriented programming languages
  • Knowledge of at least one standard verification methodology (such as VMM, OVM, or UVM)
  • Familiarity with RTL design, synthesis, and CDC analysis is a plus
  • Working knowledge of shell, Perl, and TCL scripting is a plus
  • Experience with clock domain crossing and reset architecture. 

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