Mixel is hiring.Mixel is seeking exceptional, self-driven, team members who are eager to work on cutting ed
ge projects utilizing the latest technologies and tools. If you have Mixed-Signal experience and project management experience, besides being motivated, energetic, and eager to grow in your profession, then come join our team at Mixel and experience working with teams from Silicon Valley and customers around the globe.
Successful applicants will work with highly experienced engineers on the ground floor of a growing company, developing IP cores in the areas of high-performance, low-power PHYs.
Play a critical part in Mixel’s next phase of growth and contribute to its long term success. This can be an once-in-a-lifetime opportunity for the right candidate, and can rapidly lead to larger responsibilities and rewards. Work with Mixed-signal Engineers with decades of experience, on exciting projects designing Mixed-signal CMOS IP cores and Integrated Circuits.
Join Mixel and see your designs working in new and exciting commercially available products. We are enabling the next generation of mobile platforms, IoT, automotive, and wearable.
If you are an intelligent, motivated, and hardworking engineer that would like to be part of an outstanding team, and would enjoy working in an exciting, friendly, professional, fast-paced, and technically challenging environment, then we urge you to email us your resume.
- EG_ ASIV_02
- Cairo, Egypt
- Hands-on experience with employing constrained-random coverage driven verification methodology using UVM
- Participating in deploying new methodologies to improve coverage and execution time in collaboration with other experienced engineers on the team
- Working with the design team to validate and verify any requested design changes throughout the project life cycle.
- Develop test plan from specification and architect system-level verification environments.
- Develop test-bench components and coverage metrics.
- Execute RTL/Gate level simulations and analyze results.
- Work with the mixed-signal team on the co-simulation and verification of mixed-signal IPs.
- Contribute to design/verification process automation.
- B.Sc. or M.Sc. in Electronics Engineering
- 3+ Years of experience in developing SV-based verification environments.
- Strong knowledge of Verilog, System Verilog, and object-oriented
- Computer skills required: Unix/Linux operating system
- Strong knowledge of Verilog, System Verilog, and object-oriented programming languages
- Knowledge of at least one standard verification methodology (such as VMM, OVM, or UVM)
- Familiarity with RTL design, synthesis, and CDC analysis is a plus
- Working knowledge of shell, Perl, and TCL scripting is a plus
Senior ASIC Design Engineer responsibilities include developing a thorough understanding of system-level design specifications
- New IPs requirements analysis and system/architecture definition.
- Building system-level models for validating architectural decisions/trade-offs.
- Complete leadership of projects or sub-systems covering all aspects of planning, status & milestones follow-up.
- Providing mentorship and technical leadership.
- Providing support and guidance for Post-Silicon bench testing/characterization.
- Leading and supporting technical communication channels with customers, vendors, etc...
- Introducing & implementing methodology modifications for enhancing the efficiency of Mixel’s design process & IPs robustness.
Qualifications:
- BSc in Electronics/Communication with 7+ years of experience.
- Hands-on knowledge & experience in A/MS/RF building blocks (PLLs, CDRs, Drivers, AFEs, Biasing & Power Management)
- Strong knowledge of IC design flow using Mentor & Cadence tools.
- Strong knowledge of A/MS behavioral modeling.
- Strong communication, leadership, and analytical skills.
- Experience with Matlab/Simulink is a plus.
- Experience with advanced FinFET process nodes is a plus.
Work Scope: New IPs requirements analysis and system/architecture definition. Building system-level models for validating architectural decisions/trade-offs. Complete leadership of projects or sub-sys...
- EG_ ASIV_05
- Cairo, Egypt
- Team planning and team member resource utilization.
- Hands-on experience with employing constrained-random coverage driven verification methodology using UVM
- Participating in deploying new methodologies to improve coverage and execution time in collaboration with other experienced engineers on the team
- Working with the design team to validate and verify any requested design changes throughout the project life cycle.
- Develop a thorough understanding of system-level design specifications.
- RTL Coding/Synthesis of the digital part of Mixed-Signal IPs.
- Develop behavioral models for the analog parts of Mixed-Signal IPs.
- Working with the verification team to develop advanced test plans.
- Working with the Mixed-Signal team on the co-simulation and verification of the IPs.
- Hardware verification of the digital module using cutting-edge FPGA kits.
- Coach your team members in a way that strengthens two-way communication and reinforces desired behaviors.
- Monitor the project's load on the team members and act/organize accordingly, to remove stress, or retain balance/fairness in the distribution of workload after agreement with Project Leads, and Team Manager.
- Communicating team goals and identifying areas for new training or skill checks.
- Develop the Training and Development needs for each employee, and Agree on a development plan to help them improve their performance and support the organization's success.
- Motivates others by setting a good example and appreciates/provides encouragement to the ongoing effort of the team members.
- B.Sc. or M.Sc. in Electronics Engineering
- 7+ Years of experience in developing SV-based verification environments.
- Strong knowledge of Verilog, System Verilog, and object-oriented
- Computer skills required: Unix/Linux operating system
- Strong knowledge of Verilog, System Verilog, and object-oriented programming languages
- Knowledge of at least one standard verification methodology (such as VMM, OVM, or UVM)
- Familiarity with RTL design, synthesis, and CDC analysis is a plus
- Working knowledge of shell, Perl, and TCL scripting is a plus
- Experience with clock domain crossing and reset architecture.
Digital Verification Development Senior Team Lead
- EG_MSIP_02
- Cairo, Egypt
- Contribute to the development and design of products targeting the most exciting market segments such as VR, AR, IoT, and Automotive and strive to achieve first-time silicon success
- Work in close cooperation with System Architects, Chip Architects, Digital IC designers, Physical IC Designers, Senior Mixed-Signal Designers, and Project Managers to deliver in time and according to required specifications
- Contribute to the validation and debugging of the fabricated silicon
- Work independently and methodically on analyzing design, tool, and technology problems, identifying best solutions, and implementing the solutions in a repeatable fashion that integrates well within the implementation flow
- Meet the strict quality and schedule requirements
- Produce exceptional results as an individual and team contributor
- B.Sc./M.Sc. in Electrical Engineering
- 4-9 years of experience in Mixed-Signal IC design
- Knowledge of Shell scripting/programming languages
- Knowledge of Unix/Linux operating systems
- SerDes, PLL, and CDR experience is a plus
- MIPI and DDR PHY design experience is a plus
- Project Management experience is a plus
Job Code EG_MSIP_02 Location Cairo, Egypt About the Job Contribute to the development and design of products targeting the most exciting market segments such as VR, AR, IoT, and Automotive and strive ...
- San Jose, CA
The candidate should have a MSEE or PhD EE and 15+ years of experience, with expertise in the design of PHY, SerDes, PLL, and CDR circuits. Take overall technical responsibility for multiple exciting, state of the art projects in the fast-growing interconnect IP segment. Direct the creation of the critical components that will interconnect the next generation of mobile, automotive, IoT, and VR platforms. Play a critical part in Mixel’s next phase of growth and contribute to its long-term success. The candidate will lead teams of designers and take overall responsibility of projects’ success. This can be a once-in-a-lifetime opportunity for the right candidate and can rapidly lead to larger responsibilities and rewards.
Key Responsibilities- Lead a team developing Mixed Signal IP products.
- Work in close cooperation with Mixed Signal designers, Digital designers, and Physical Designers to deliver in time and according to required specifications.
- Conduct, and contribute to Front-end and Back-end design reviews.
- Contribute to the validation and debugging of fabricated silicon.
- Work independently and methodically on analyzing design, tool, and technology problems, identifying best solutions, and implementing the solutions in a repeatable fashion that integrates well within the implementation flow.
- Meet strict quality and schedule requirements.
- Collaborate cross-functionally with Marketing, Sales & Operations.
- Master’s degree in Electrical Engineering
- PhD degree is a Plus
- Years of experience in the same field: 15+ Years of experience in Mixed-Signal IC design
- Skills required:
- SerDes, PLL, and CDR experience
- Project Management Experience
The candidate should have a MSEE or PhD EE and 15+ years of experience, with expertise in the design of PHY, SerDes, PLL, and CDR circuits.
- SJ_MSIP_02
- San Jose, CA
- Take overall technical responsibility for exciting, state of the art projects in the explosive mobile PHY market
- Create the critical components that will interconnect the next generation of mobile platforms such as smart phones and tablets, a market segment where Mixel is the clear leader
- Work in close cooperation with Mixed-Signal Designers, Digital Designers, and Physical Designers to deliver in time and according to required specifications
- Conduct, and contribute in, front-end and back-end design reviews
- Contribute to the validation and debugging of the fabricated silicon
- Work independently and methodically on analyzing design, tool, and technology problems, identifying best solutions, and implementing the solutions in a repeatable fashion that integrates well within the implementation flow
- Meet strict quality and schedule requirements
- Play a critical part in Mixel’s next phase of growth and contribute to its long-term success
- The candidate will take overall responsibility of projects’ success
- This can be a once-in-a-lifetime opportunity for the right candidate and can rapidly lead to larger responsibilities and rewards
- MSEE or PhD EE and 5-10 years of experience
- Expertise in the design of PHY, SerDes, PLL, and CDR
- Project Management experience
- Strong knowledge of Shell scripting/programming languages
- Strong knowledge of Unix/Linux operating systems
Mixed-Signal Design Engineer responsibilities include taking overall technical responsibility for exciting, state of the art projects in the explosive mobile PHY market
- SJ_MSIP_01
- San Jose, CA
- Participate in design, porting, layout, layout review, verification, and enhancement of mixed-signal circuits such as PLLs, DLL, Transceivers, PHYs, CDRs, Bias circuits, and related blocks
- Contribute as a team player in development and design of products targeting most exciting market segments such as VR, AR, IoT, and Automotive and strive to achieve first-time silicon success
- Work in close cooperation with System Architects, Chip Architects, Digital IC designers and Physical IC Designers, Senior Mixed-Signal Designers and Project Manager to deliver in time and according to required specifications
- Responsible for the schematic entry, simulation, and verification of relevant analog IC blocks
- Generate the required documentation and contribute to the validation and debugging of the fabricated silicon
- Work independently and methodically on analyzing design, tool, and technology problems, identifying best solutions, and implementing the solutions in a repeatable fashion that integrates well within the implementation flow
- Meet strict quality and schedule requirements
- Produce exceptional results as an individual and team contributor
- B.Sc./M.Sc. in Electrical Engineering
- 0-4 Years of experience in Mixed-Signal IC design
- Knowledge of Shell scripting/programming languages
- Knowledge of Unix/Linux operating systems
- SerDes, PLL, and CDR experience is a plus
- MIPI and DDR PHY design experience is a plus
Mixed-Signal Circuit Design Engineer responsibilities include participating in design, porting, layout, layout review, verification and enhancement of mixed-signal circuits such as PLLs, DLL, Transcei...