Mixel is hiring.Mixel is seeking exceptional, self-driven, team members who are eager to work on cutting ed
ge projects utilizing the latest technologies and tools. If you have Mixed-Signal experience and project management experience, besides being motivated, energetic, and eager to grow in your profession, then come join our team at Mixel and experience working with teams from Silicon Valley and customers around the globe.
Successful applicants will work with highly experienced engineers on the ground floor of a growing company, developing IP cores in the areas of high-performance, low-power PHYs.
Play a critical part in Mixel’s next phase of growth and contribute to its long term success. This can be an once-in-a-lifetime opportunity for the right candidate, and can rapidly lead to larger responsibilities and rewards. Work with Mixed-signal Engineers with decades of experience, on exciting projects designing Mixed-signal CMOS IP cores and Integrated Circuits.
Join Mixel and see your designs working in new and exciting commercially available products. We are enabling the next generation of mobile platforms, IoT, automotive, and wearable.
If you are an intelligent, motivated, and hardworking engineer that would like to be part of an outstanding team, and would enjoy working in an exciting, friendly, professional, fast-paced, and technically challenging environment, then we urge you to email us your resume.
Job Code
- EG_DIG_03
- Cairo, Egypt
- Develop a thorough understanding of system-level design specifications
- Derive top-level digital architecture planning
- Verilog RTL Coding, Synthesis, Simulation of the digital IPs
- Working with the verification team to develop advanced test plans
- Oversee static timing analysis and timing closure
- Hardware verification of the digital module using cutting edge FPGA kits
- Manage support of customer applications and use-cases
- Contribute to the validation and debugging of the fabricated silicon
- B.Sc. or M.Sc. in Electronics Engineering
- 5+ Years of experience in VLSI Digital Design
- Technical leadership and project management skills
- Excellent verbal and written communication skills are required
- Excellent follow-up and persistence
- Strong technical judgement and decision making abilities
- Expert knowledge in Verilog RTL coding techniques
- Strong Knowledge of ASIC/FPGA design flows including RTL synthesis, and timing closure of high speed digital designs
- Experience with clock domain crossing and reset architecture
- Knowledge of System Verilog, RTL/gate verification techniques
- Strong knowledge of Shell, Perl, Python and TCL scripting
- Strong knowledge of Unix/Linux operating system
Digital Staff Engineer responsibilities include developing a thorough understanding of system-level design specifications
Job Code
- EG_DIG_04
- Cairo, Egypt
- Team planning, resource utilization of projects’ load on the team & act/organize accordingly
- Coaching, monitoring & assessing performance of team members in a way that strengthens two-way communication and reinforces desired behaviors & set training & Development plans
- Work & cooperate closely with the digital design team and Mixed Signal designers to deliver in time and according to required specifications
- Conduct, and contribute to internal design reviews to ensure compliance to the company digital design process
- Develop a thorough understanding of system-level design specifications
- Derive digital design life-cycle from concept phase to product realization
- Contribute to the validation and debugging of the fabricated silicon
- Work independently & with the team and methodically on analyzing design, tool, and technology problems, identifying best solutions, and implementing the solutions in a repeatable fashion that integrates well within the implementation flow
- Meet strict quality and schedule requirements
- B.Sc. or M.Sc. in Electronics Engineering
- 6+ Years of experience in VLSI Digital Design
- Team leadership and project management skills
- Excellent verbal and written communication skills are required
- Excellent follow-up and persistence
- Strong technical judgement and decision making abilities
- Expert knowledge in Verilog RTL coding techniques
- Strong Knowledge of ASIC/FPGA design flows including RTL synthesis, and timing closure of high speed digital designs
- Experience with clock domain crossing and reset architecture
- Knowledge of System Verilog, RTL/gate verification techniques
- Strong knowledge of Shell, Perl, Python and TCL scripting
- Strong knowledge of Unix/Linux operating system
Digital Team Lead responsibilities include team planning, resource utilization of projects’ load on the team, & acting/organizing accordingly
Job Code
- EG_DIG_05
- Cairo, Egypt
- Develop a thorough understanding of system-level design specifications
- Derive top-level digital architecture planning
- Verilog RTL Coding, Synthesis, Simulation of the digital IPs
- Working with the verification team to develop advanced test plans
- Oversee static timing analysis and timing closure
- Hardware verification of the digital module using cutting edge FPGA kits
- Manage support of customer applications and use-cases
- Contribute to the validation and debugging of the fabricated silicon
- B.Sc. or M.Sc. in Electronics Engineering
- 8+ Years of experience in VLSI Digital Design
- Technical leadership and project management skills
- Excellent verbal and written communication skills are required
- Excellent follow-up and persistence
- Strong technical judgement and decision making abilities
- Expert knowledge in Verilog RTL coding techniques
- Strong Knowledge of ASIC/FPGA design flows including RTL synthesis, and timing closure of high speed digital designs
- Experience with clock domain crossing and reset architecture
- Knowledge of System Verilog, RTL/gate verification techniques
- Strong knowledge of Shell, Perl, Python and TCL scripting
- Strong knowledge of Unix/Linux operating system
Digital Senior Staff Engineer responsibilities include developing a thorough understanding of system-level design specifications
Job Code
- EG_DIG_01
- Cairo, Egypt
- Develop a thorough understanding of system-level design specifications
- Verilog RTL Coding, Synthesis, Simulation of the digital IPs
- Develop advanced verification environment and test-bench components
- Hardware verification of the digital module using cutting edge FPGA kits
- Gate level verification of digital IPs
- Bachelor’s degree of Electronics Engineering. Master’s Degree is a plus
- 0-3 Years of experience in VLSI Digital Design/Verification, gate verification techniques is a plus
- Strong knowledge of Verilog RTL design/simulation
- Knowledge of ASIC/FPGA design flows including RTL Synthesis, Place and Route, and Timing Sign-off
- Knowledge of Unix/Linux operating system is a plus
- Knowledge of shell scripting/programming languages is a plus
Digital Design Engineer responsibilities include developing a thorough understanding of system-level design specifications
Job Code
- EG_DIG_04
- Cairo, Egypt
- Team planning, resource utilization of projects’ load on the team & act/organize accordingly
- Coaching, monitoring & assessing performance of team members in a way that strengthens two-way communication and reinforces desired behaviors & set training & Development plans
- Work & cooperate closely with the digital design team and Mixed Signal designers to deliver in time and according to required specifications
- Conduct, and contribute to internal design reviews to ensure compliance to the company digital design process
- Develop a thorough understanding of system-level design specifications
- Derive digital design life-cycle from concept phase to product realization
- Contribute to the validation and debugging of the fabricated silicon
- Work independently & with the team and methodically on analyzing design, tool, and technology problems, identifying best solutions, and implementing the solutions in a repeatable fashion that integrates well within the implementation flow
- Meet strict quality and schedule requirements
- B.Sc. or M.Sc. in Electronics Engineering
- 6+ Years of experience in VLSI Digital Design
- Team leadership and project management skills
- Excellent verbal and written communication skills are required
- Excellent follow-up and persistence
- Strong technical judgement and decision making abilities
- Expert knowledge in Verilog RTL coding techniques
- Strong Knowledge of ASIC/FPGA design flows including RTL synthesis, and timing closure of high speed digital designs
- Experience with clock domain crossing and reset architecture
- Knowledge of System Verilog, RTL/gate verification techniques
- Strong knowledge of Shell, Perl, Python and TCL scripting
- Strong knowledge of Unix/Linux operating system
Digital Team Lead responsibilities include team planning, resource utilization of projects’ load on the team, & acting/organizing accordingly
Job Code
- EG_ ASIP_04
- Cairo, Egypt
- Team planning, resource utilization of projects’ load on the team & act/organize accordingly
- Coaching, monitoring & assessing performance of team members in a way that strengthens two-way communication and reinforces desired behaviors & set training & Development plans
- Work & cooperate closely with the ASIC design team and Mixed Signal designers to deliver in time and according to required specifications
- Conduct, and contribute to internal design reviews to ensure compliance to the company ASIC design process
- Develop a thorough understanding of system-level design specifications
- Derive digital design life-cycle from concept phase to product realization
- Contribute to the validation and debugging of the fabricated silicon
- Work independently & with the team and methodically on analyzing design, tool, and technology problems, identifying best solutions, and implementing the solutions in a repeatable fashion that integrates well within the implementation flow
- Meet strict quality and schedule requirements
- B.Sc. or M.Sc. in Electronics Engineering
- 8+ Years of experience in VLSI Digital Design
- Team leadership and project management skills
- Excellent verbal and written communication skills are required
- Excellent follow-up and persistence
- Strong technical judgement and decision making abilities
- Expert knowledge in Verilog RTL coding techniques
- Strong Knowledge of ASIC/FPGA design flows including RTL synthesis, and timing closure of high speed digital designs
- Experience with clock domain crossing and reset architecture
- Knowledge of System Verilog, RTL/gate verification techniques
- Strong knowledge of Shell, Perl, Python and TCL scripting
- Strong knowledge of Unix/Linux operating system.
ASIC Team Lead responsibilities include team planning, resource utilization of projects’ load on the team & act/organize accordingly
Job Code
- EG_MSIP_03
- Cairo, Egypt
- Contribute in technically leading a team developing Mixed Signal IP products.
- Contribute to the development and design of products targeting the most exciting market segments such as VR, AR, IoT, and Automotive and strive to achieve first-time silicon success
- Work in close cooperation with System Architects, Chip Architects, Digital IC designers, Physical IC Designers, Senior Mixed-Signal Designers, and Project Managers to deliver in time and according to required specifications
- Contribute to the validation and debugging of the fabricated silicon
- Work independently and methodically on analyzing design, tool, and technology problems, identifying best solutions, and implementing the solutions in a repeatable fashion that integrates well within the implementation flow
- Meet the strict quality and schedule requirements
- Produce exceptional results as an individual and team contributor
- B.Sc./M.Sc. in Electrical Engineering
- 5+ years of experience in Mixed-Signal IC design
- Knowledge of Shell scripting/programming languages
- Knowledge of Unix/Linux operating systems
- SerDes, PLL, and CDR experience is a plus
- MIPI and DDR PHY design experience is a plus
- Project Management experience is a plus
Job Code EG_MSIP_03 Location Cairo, Egypt About the Job Contribute in technically leading a team developing Mixed Signal IP products. Contribute to the development and design of products targeting the...
Work Scope:
- New IPs requirements analysis and system/architecture definition.
- Building system-level models for validating architectural decisions/trade-offs.
- Complete leadership of projects or sub-systems covering all aspects of planning, status & milestones follow-up.
- Providing mentorship and technical leadership.
- Providing support and guidance for Post-Silicon bench testing/characterization.
- Leading and supporting technical communication channels with customers, vendors, etc...
- Introducing & implementing methodology modifications for enhancing the efficiency of Mixel’s design process & IPs robustness.
Qualifications:
- BSc in Electronics/Communication with 5+ years of experience.
- Hands-on knowledge & experience in A/MS/RF building blocks (PLLs, CDRs, Drivers, AFEs, Biasing & Power Management)
- Strong knowledge of IC design flow using Mentor & Cadence tools.
- Strong knowledge of A/MS behavioral modeling.
- Strong communication, leadership, and analytical skills.
- Experience with Matlab/Simulink is a plus.
- Experience with advanced FinFET process nodes is a plus.
CAD Senior Engineer responsibilities include developing, enhancing, and maintaining a wide variety of EDA tool infrastructure and flows
Work Scope:
- New IPs requirements analysis and system/architecture definition.
- Building system-level models for validating architectural decisions/trade-offs.
- Complete leadership of projects or sub-systems covering all aspects of planning, status & milestones follow-up.
- Providing mentorship and technical leadership.
- Providing support and guidance for Post-Silicon bench testing/characterization.
- Leading and supporting technical communication channels with customers, vendors, etc...
- Introducing & implementing methodology modifications for enhancing the efficiency of Mixel’s design process & IPs robustness.
Qualifications:
- BSc in Electronics/Communication with 7+ years of experience.
- Hands-on knowledge & experience in A/MS/RF building blocks (PLLs, CDRs, Drivers, AFEs, Biasing & Power Management)
- Strong knowledge of IC design flow using Mentor & Cadence tools.
- Strong knowledge of A/MS behavioral modeling.
- Strong communication, leadership, and analytical skills.
- Experience with Matlab/Simulink is a plus.
- Experience with advanced FinFET process nodes is a plus.
CAD Senior Engineer responsibilities include developing, enhancing, and maintaining a wide variety of EDA tool infrastructure and flows
Work Scope:
- New IPs requirements analysis and system/architecture definition.
- Building system-level models for validating architectural decisions/trade-offs.
- Complete leadership of projects or sub-systems covering all aspects of planning, status & milestones follow-up.
- Providing mentorship and technical leadership.
- Providing support and guidance for Post-Silicon bench testing/characterization.
- Leading and supporting technical communication channels with customers, vendors, etc...
- Introducing & implementing methodology modifications for enhancing the efficiency of Mixel’s design process & IPs robustness.
Qualifications:
- BSc in Electronics/Communication with 10+ years of experience.
- Hands-on knowledge & experience in A/MS/RF building blocks (PLLs, CDRs, Drivers, AFEs, Biasing & Power Management)
- Strong knowledge of IC design flow using Mentor & Cadence tools.
- Strong knowledge of A/MS behavioral modeling.
- Strong communication, leadership, and analytical skills.
- Experience with Matlab/Simulink is a plus.
- Experience with advanced FinFET process nodes is a plus.
CAD Senior Engineer responsibilities include developing, enhancing, and maintaining a wide variety of EDA tool infrastructure and flows