Mixel is hiring.Mixel is seeking exceptional, self-driven, team members who are eager to work on cutting ed
ge projects utilizing the latest technologies and tools. If you have Mixed-Signal experience and project management experience, besides being motivated, energetic, and eager to grow in your profession, then come join our team at Mixel and experience working with teams from Silicon Valley and customers around the globe.
Successful applicants will work with highly experienced engineers on the ground floor of a growing company, developing IP cores in the areas of high-performance, low-power PHYs.
Play a critical part in Mixel’s next phase of growth and contribute to its long term success. This can be an once-in-a-lifetime opportunity for the right candidate, and can rapidly lead to larger responsibilities and rewards. Work with Mixed-signal Engineers with decades of experience, on exciting projects designing Mixed-signal CMOS IP cores and Integrated Circuits.
Join Mixel and see your designs working in new and exciting commercially available products. We are enabling the next generation of mobile platforms, IoT, automotive, and wearable.
If you are an intelligent, motivated, and hardworking engineer that would like to be part of an outstanding team, and would enjoy working in an exciting, friendly, professional, fast-paced, and technically challenging environment, then we urge you to email us your resume.
Job Code
- EG_DIG_04
- Cairo, Egypt
- Team planning, resource utilization of projects’ load on the team & act/organize accordingly
- Coaching, monitoring & assessing performance of team members in a way that strengthens two-way communication and reinforces desired behaviors & set training & Development plans
- Work & cooperate closely with the digital design team and Mixed Signal designers to deliver in time and according to required specifications
- Conduct, and contribute to internal design reviews to ensure compliance to the company digital design process
- Develop a thorough understanding of system-level design specifications
- Derive digital design life-cycle from concept phase to product realization
- Contribute to the validation and debugging of the fabricated silicon
- Work independently & with the team and methodically on analyzing design, tool, and technology problems, identifying best solutions, and implementing the solutions in a repeatable fashion that integrates well within the implementation flow
- Meet strict quality and schedule requirements
- B.Sc. or M.Sc. in Electronics Engineering
- 6+ Years of experience in VLSI Digital Design
- Team leadership and project management skills
- Excellent verbal and written communication skills are required
- Excellent follow-up and persistence
- Strong technical judgement and decision making abilities
- Expert knowledge in Verilog RTL coding techniques
- Strong Knowledge of ASIC/FPGA design flows including RTL synthesis, and timing closure of high speed digital designs
- Experience with clock domain crossing and reset architecture
- Knowledge of System Verilog, RTL/gate verification techniques
- Strong knowledge of Shell, Perl, Python and TCL scripting
- Strong knowledge of Unix/Linux operating system
Digital Team Lead responsibilities include team planning, resource utilization of projects’ load on the team, & acting/organizing accordingly
Job Code
- EG_ ASIP_02
- Cairo, Egypt
- Develop a thorough understanding of system-level design specifications
- RTL Coding/Synthesis of the digital part of Mixed Signal IPs
- Develop behavioral models for the analog parts of Mixed Signal IPs
- Working with the verification team to develop advanced test plans
- Working with the mixed signal team on the co-simulation and verification of the IPs
- Hardware verification of the digital module using cutting edge FPGA kits
- B.Sc. or M.Sc. in Electronics Engineering
- 3+ Years of experience in VLSI Digital Design
- Strong knowledge of Verilog RTL design/simulation, gate verification techniques is a plus
- ASIC/FPGA design flows including RTL synthesis, and timing sign-off
- Experience with clock domain crossing and reset architecture
- Working knowledge of Shell, Perl, and TCL scripting
- Unix/Linux operating system
Senior ASIC Design Engineer responsibilities include developing a thorough understanding of system-level design specifications
Job Code
- EG_ ASIP_04
- Cairo, Egypt
- Team planning, resource utilization of projects’ load on the team & act/organize accordingly
- Coaching, monitoring & assessing performance of team members in a way that strengthens two-way communication and reinforces desired behaviors & set training & Development plans
- Work & cooperate closely with the ASIC design team and Mixed Signal designers to deliver in time and according to required specifications
- Conduct, and contribute to internal design reviews to ensure compliance to the company ASIC design process
- Develop a thorough understanding of system-level design specifications
- Derive digital design life-cycle from concept phase to product realization
- Contribute to the validation and debugging of the fabricated silicon
- Work independently & with the team and methodically on analyzing design, tool, and technology problems, identifying best solutions, and implementing the solutions in a repeatable fashion that integrates well within the implementation flow
- Meet strict quality and schedule requirements
- B.Sc. or M.Sc. in Electronics Engineering
- 8+ Years of experience in VLSI Digital Design
- Team leadership and project management skills
- Excellent verbal and written communication skills are required
- Excellent follow-up and persistence
- Strong technical judgement and decision making abilities
- Expert knowledge in Verilog RTL coding techniques
- Strong Knowledge of ASIC/FPGA design flows including RTL synthesis, and timing closure of high speed digital designs
- Experience with clock domain crossing and reset architecture
- Knowledge of System Verilog, RTL/gate verification techniques
- Strong knowledge of Shell, Perl, Python and TCL scripting
- Strong knowledge of Unix/Linux operating system.
ASIC Team Lead responsibilities include team planning, resource utilization of projects’ load on the team & act/organize accordingly
Job Code
- EG_LAIP_04
- Cairo, Egypt
- Team planning and team member resource utilization.
- Conduct weekly meetings with his team members to follow up on the progress of assigned tasks.
- Attend lead status meetings where the different aspects of the projects are discussed & provide clear status of his team’s assigned projects.
- Resolving all technical and managerial issues within the team.
- Monitor the project's load on the team members and act/organize accordingly, to remove stress, or retain balance/fairness in the distribution of workload after agreement with Project Leads, and Team Manager.
- Perform continuous mentoring through proper performance review standards and process, sets goals, areas for new training, skill checks, the development plan for each team member to help them improve their performance to support the organization's success.
- B.Sc./M.Sc. in Electronics Engineering
- 6+ Years of experience in custom IC layout techniques or EDA tools or relevant experience
- Knowledge of EDA tools used in analog IC design
- Knowledge of Physical verification DRC/LVS/DFM/ERC/MRC/ESD/IO
- Knowledge of Analog design techniques
- Strong knowledge of Unix/Linux operating system
- Project management experience is required.
- Strong knowledge of Shell scripting/programming languages
Job Code EG_LAIP_04 Location Cairo, Egypt About the Job Team planning and team member resource utilization. Conduct weekly meetings with his team members to follow up on the progress of assigned tasks...
Job Code
Job Requirements
- EG_ ASIV_04
- Cairo, Egypt
- Team planning and team member resource utilization.
- Hands-on experience with employing constrained-random coverage driven verification methodology using UVM
- Participating in deploying new methodologies to improve coverage and execution time in collaboration with other experienced engineers on the team
- Working with the design team to validate and verify any requested design changes throughout the project life cycle.
- Develop a thorough understanding of system-level design specifications.
- RTL Coding/Synthesis of the digital part of Mixed-Signal IPs.
- Develop behavioral models for the analog parts of Mixed-Signal IPs.
- Working with the verification team to develop advanced test plans.
- Working with the Mixed-Signal team on the co-simulation and verification of the IPs.
- Hardware verification of the digital module using cutting-edge FPGA kits.
- Coach your team members in a way that strengthens two-way communication and reinforces desired behaviors.
- Monitor the project's load on the team members and act/organize accordingly, to remove stress, or retain balance/fairness in the distribution of workload after agreement with Project Leads, and Team Manager.
- Communicating team goals and identifying areas for new training or skill checks.
- Develop the Training and Development needs for each employee, and Agree on a development plan to help them improve their performance and support the organization's success.
- Motivates others by setting a good example and appreciates/provides encouragement to the ongoing effort of the team members.
- B.Sc. or M.Sc. in Electronics Engineering
- 5+ Years of experience in developing SV-based verification environments.
- Strong knowledge of Verilog, System Verilog, and object-oriented
- Computer skills required: Unix/Linux operating system
- Strong knowledge of Verilog, System Verilog, and object-oriented programming languages
- Knowledge of at least one standard verification methodology (such as VMM, OVM, or UVM)
- Familiarity with RTL design, synthesis, and CDC analysis is a plus
- Working knowledge of shell, Perl, and TCL scripting is a plus
- Experience with clock domain crossing and reset architecture.
Digital Verification Development Team Lead
Job Code
- ASIV_01
- Cairo, Egypt
- Hands-on experience with employing constrained-random coverage driven verification methodology using UVM.
- Working with the design team to validate and verify any requested design changes throughout the project life cycle.
- Develop test plan from specification and architect system-level verification environments
- Develop test-bench components, and coverage metrics
- Execute RTL/Gate level simulations and analyze results
- Work with the mixed-signal team on the co-simulation and verification of mixed-signal IPs
- Contribute to design/verification process automation
- B.Sc. in Electronics/Computer Engineering
- Years of experience in the same field: 0-4 Years of experience in developing SV-based verification environments
- English Language Proficiency: Fluency
- Computer skills required: Unix/Linux operating system
- Strong knowledge of Verilog, System Verilog, and object-oriented programming languages
- Knowledge of at least one standard verification methodology (such as VMM, OVM, or UVM)
- Familiarity with RTL design, synthesis, and CDC analysis is a plus
- Working knowledge of shell, Perl, and TCL scripting is a plus
Develop test plans from specifications, architect system level verification environments, test-bench components, and coverage metrics
Job Code
Job Requirements
- EG_ ASIV_03
- Cairo, Egypt
- Hands-on experience with employing constrained-random coverage driven verification methodology using UVM
- Participating in deploying new methodologies to improve coverage and execution time in collaboration with other experienced engineers on the team
- Working with the design team to validate and verify any requested design changes throughout the project life cycle.
- Develop a thorough understanding of system-level design specifications.
- RTL Coding/Synthesis of the digital part of Mixed-Signal IPs.
- Develop behavioral models for the analog parts of Mixed-Signal IPs.
- Working with the verification team to develop advanced test plans.
- Working with the Mixed-Signal team on the co-simulation and verification of the IPs.
- Hardware verification of the digital module using cutting-edge FPGA kits.
- B.Sc. or M.Sc. in Electronics Engineering
- 5+ Years of experience in developing SV-based verification environments.
- Strong knowledge of Verilog, System Verilog, and object-oriented
- Computer skills required: Unix/Linux operating system
- Strong knowledge of Verilog, System Verilog, and object-oriented programming languages
- Knowledge of at least one standard verification methodology (such as VMM, OVM, or UVM)
- Familiarity with RTL design, synthesis, and CDC analysis is a plus
- Working knowledge of shell, Perl, and TCL scripting is a plus
- Experience with clock domain crossing and reset architecture.
Digital Verification Development Staff Engineer
Job Code
- EG_ ASIV_02
- Cairo, Egypt
- Hands-on experience with employing constrained-random coverage driven verification methodology using UVM
- Participating in deploying new methodologies to improve coverage and execution time in collaboration with other experienced engineers on the team
- Working with the design team to validate and verify any requested design changes throughout the project life cycle.
- Develop test plan from specification and architect system-level verification environments.
- Develop test-bench components and coverage metrics.
- Execute RTL/Gate level simulations and analyze results.
- Work with the mixed-signal team on the co-simulation and verification of mixed-signal IPs.
- Contribute to design/verification process automation.
- B.Sc. or M.Sc. in Electronics Engineering
- 3+ Years of experience in developing SV-based verification environments.
- Strong knowledge of Verilog, System Verilog, and object-oriented
- Computer skills required: Unix/Linux operating system
- Strong knowledge of Verilog, System Verilog, and object-oriented programming languages
- Knowledge of at least one standard verification methodology (such as VMM, OVM, or UVM)
- Familiarity with RTL design, synthesis, and CDC analysis is a plus
- Working knowledge of shell, Perl, and TCL scripting is a plus
Senior ASIC Design Engineer responsibilities include developing a thorough understanding of system-level design specifications
Work Scope:
- New IPs requirements analysis and system/architecture definition.
- Building system-level models for validating architectural decisions/trade-offs.
- Complete leadership of projects or sub-systems covering all aspects of planning, status & milestones follow-up.
- Providing mentorship and technical leadership.
- Providing support and guidance for Post-Silicon bench testing/characterization.
- Leading and supporting technical communication channels with customers, vendors, etc...
- Introducing & implementing methodology modifications for enhancing the efficiency of Mixel’s design process & IPs robustness.
Qualifications:
- BSc in Electronics/Communication with 7+ years of experience.
- Hands-on knowledge & experience in A/MS/RF building blocks (PLLs, CDRs, Drivers, AFEs, Biasing & Power Management)
- Strong knowledge of IC design flow using Mentor & Cadence tools.
- Strong knowledge of A/MS behavioral modeling.
- Strong communication, leadership, and analytical skills.
- Experience with Matlab/Simulink is a plus.
- Experience with advanced FinFET process nodes is a plus.
Work Scope: New IPs requirements analysis and system/architecture definition. Building system-level models for validating architectural decisions/trade-offs. Complete leadership of projects or sub-sys...
Job Code
Job Requirements
- EG_ ASIV_05
- Cairo, Egypt
- Team planning and team member resource utilization.
- Hands-on experience with employing constrained-random coverage driven verification methodology using UVM
- Participating in deploying new methodologies to improve coverage and execution time in collaboration with other experienced engineers on the team
- Working with the design team to validate and verify any requested design changes throughout the project life cycle.
- Develop a thorough understanding of system-level design specifications.
- RTL Coding/Synthesis of the digital part of Mixed-Signal IPs.
- Develop behavioral models for the analog parts of Mixed-Signal IPs.
- Working with the verification team to develop advanced test plans.
- Working with the Mixed-Signal team on the co-simulation and verification of the IPs.
- Hardware verification of the digital module using cutting-edge FPGA kits.
- Coach your team members in a way that strengthens two-way communication and reinforces desired behaviors.
- Monitor the project's load on the team members and act/organize accordingly, to remove stress, or retain balance/fairness in the distribution of workload after agreement with Project Leads, and Team Manager.
- Communicating team goals and identifying areas for new training or skill checks.
- Develop the Training and Development needs for each employee, and Agree on a development plan to help them improve their performance and support the organization's success.
- Motivates others by setting a good example and appreciates/provides encouragement to the ongoing effort of the team members.
- B.Sc. or M.Sc. in Electronics Engineering
- 7+ Years of experience in developing SV-based verification environments.
- Strong knowledge of Verilog, System Verilog, and object-oriented
- Computer skills required: Unix/Linux operating system
- Strong knowledge of Verilog, System Verilog, and object-oriented programming languages
- Knowledge of at least one standard verification methodology (such as VMM, OVM, or UVM)
- Familiarity with RTL design, synthesis, and CDC analysis is a plus
- Working knowledge of shell, Perl, and TCL scripting is a plus
- Experience with clock domain crossing and reset architecture.
Digital Verification Development Senior Team Lead