Job Code

• EG_ ASIP_04

Location

• Cairo, Egypt

About the Job

• Team planning, resource utilization of projects’ load on the team & act/organize accordingly
• Coaching, monitoring & assessing performance of team members in a way that strengthens two-way communication and reinforces desired behaviors & set training & Development plans
• Work & cooperate closely with the ASIC design team and Mixed Signal designers to deliver in time and according to required specifications
• Conduct, and contribute to internal design reviews to ensure compliance to the company ASIC design process
• Develop a thorough understanding of system-level design specifications
• Derive digital design life-cycle from concept phase to product realization
• Contribute to the validation and debugging of the fabricated silicon
• Work independently & with the team and methodically on analyzing design, tool, and technology problems, identifying best solutions, and implementing the solutions in a repeatable fashion that integrates well within the implementation flow
• Meet strict quality and schedule requirements

Job Requirements

• B.Sc. or M.Sc. in Electronics Engineering
• 8+ Years of experience in VLSI Digital Design
• Team leadership and project management skills
• Excellent verbal and written communication skills are required
• Excellent follow-up and persistence
• Strong technical judgement and decision making abilities
• Expert knowledge in Verilog RTL coding techniques
• Strong Knowledge of ASIC/FPGA design flows including RTL synthesis, and timing closure of high speed digital designs
• Experience with clock domain crossing and reset architecture
• Knowledge of System Verilog, RTL/gate verification techniques
• Strong knowledge of Shell, Perl, Python and TCL scripting
• Strong knowledge of Unix/Linux operating system.