Location

• San Jose, CA

About the Job

The candidate should have a MSEE or PhD EE and 15+ years of experience, with expertise in the design of PHY, SerDes, PLL, and CDR circuits. Take overall technical responsibility for multiple exciting, state of the art projects in the fast-growing interconnect IP segment. Direct the creation of the critical components that will interconnect the next generation of mobile, automotive, IoT, and VR platforms. Play a critical part in Mixel’s next phase of growth and contribute to its long-term success. The candidate will lead teams of designers and take overall responsibility of projects’ success. This can be a once-in-a-lifetime opportunity for the right candidate and can rapidly lead to larger responsibilities and rewards. 

Key Responsibilities 

• Lead a team developing Mixed Signal IP products.
• Work in close cooperation with Mixed Signal designers, Digital designers, and Physical Designers to deliver in time and according to required specifications.
• Conduct, and contribute to Front-end and Back-end design reviews.
• Contribute to the validation and debugging of fabricated silicon.
• Work independently and methodically on analyzing design, tool, and technology problems, identifying best solutions, and implementing the solutions in a repeatable fashion that integrates well within the implementation flow.
• Meet strict quality and schedule requirements.
• Collaborate cross-functionally with Marketing, Sales & Operations.

Job Requirements

• Master’s degree in Electrical Engineering 
  • PhD degree is a Plus
• Years of experience in the same field: 15+ Years of experience in Mixed-Signal IC design 
• Skills required:  
  • SerDes, PLL, and CDR experience 
• Project Management Experience