Digital Senior Engineer

Full-Time
Egypt
Posted 2 years ago

Job Code

  • EG_DIG_02

Location

  • Cairo, Egypt

About the Job

  • Develop a thorough understanding of system-level design specifications
  • Verilog RTL Coding, Synthesis, Simulation of the digital IPs
  • Working with the verification team to develop advanced test plans
  • Hardware verification of the digital module using cutting edge FPGA kits
  • Gate level verification of digital IPs
  • Support static timing analysis and timing closure activities

Job Requirements

  • B.Sc. or M.Sc. in Electronics Engineering
  • 3+ Years of experience in VLSI Digital Design
  • Strong knowledge of Verilog RTL design/simulation, gate verification techniques is a plus
  • ASIC/FPGA design flows including RTL synthesis, and timing sign-off
  • Experience with clock domain crossing and reset architecture
  • Working knowledge of Shell, Perl, and TCL scripting
  • Unix/Linux operating system

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