MIPI Cores

The Mixed-Signal Physical Layer (PHY) is the cornerstone of the MIPI standard’s ability to deliver high data rate at low-power. Mixel delivers silicon-proven MIPI PHYs NOW and our customers are going into production with their advanced products incorporating Mixel’s MIPI IP cores.


Mixel is a Contributing member to the MIPI Alliance since 2006 and is an active contributor to the MIPI PHY working group, participating in the development of the MIPI PHY specification developments.

We provide a complete MIPI solution including the PHY, the Controller, and a development platform.

The D-PHY, C-PHY, and the M-PHY are three different MIPI PHYs, specifically targeted at lower-power application such as mobile, IoT, wearables, and automotive. They operate over a very wide range of data-rates and support multiple power modes so mobile suppliers can deliver fast application response while preserving battery life. Their serial architectures with both a source synchronous separate clock and an embedded clock provide designers with choices from simplicity to high performance. For more information on Mixel’s D-PHY, C-PHY, and M-PHY follow the links on this page.

MIPI PHY Specification and Other Media Specs

* MIPI(™) word marks and logos are trademarks owned by MIPI Alliance, Inc. and any use of such marks by Mixel Inc. is under license. Other trademarks and trade names are those of their respective owners.